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final pu b lication# 16511 r e v : b amendment/ 0 issue date : m a y 1994 1 AM79C100 t wisted- p air etherne t t ransceiver plus (tpex plus) distinctive char a cteristics n cmos d e vice p ro vides ieee 802.3-compliant operation and l o w operating current f r om a single + 5 v supp l y n p o wer d o wn mode f or reduced p o wer consumption in battery-p o wered applications n a utomatic twisted-pair link integrity n pin-selectable twisted-pair receive polarity detection and automatic i n ve r sion of the receive signal . p olarity indication output pin can direct l y drive an le d . n pin-selectable twisted-pair link integrity test capability con f orming to the ieee 802.3 standa r d . link status pin can direct l y drive an le d . n t ransmit , receive , and collision status indications a v ailable on separate , dedicated pins n outputs can direct l y drive leds with pulses stretched to ensure led visibility n internal twisted-pair transmitter digital predisto r tion ci r cuit to reduce medium-induced jitter n pin-selectable sq e t est (hea r tbeat) enable n a ui loopba c k , jabber cont r ol , and sq e t est functions comp l y with the 10 b ase-t standa r d n use r -selectable loopba c k operations n pin-selectable twisted-pair receive threshold p r ogramming f or e xtended distance line lengths general description the am79c10 0 t wisted- p air ethe r ne t t ranscei v er plus (tpex plus) is an integrated circuit that implements the medium attachment unit (m a u) functions f or the twisted-pair medium, as speci?d b y the supplement to the ieee 802.3 standard ( t ype 10base-t) . this de- vice pr o vides the necessa r y elect r ical and functional inter f ace between the ieee 802.3 standard attachment unit inter f ace ( a ui) and the twisted-pair ca b l e . a netwo r k based on the 10base-t standard can use unshielded twisted-pair ca b le s , pr o viding an economi- cal solution to net w o r king b y all o wing the use of e xisting telephone wiring . the AM79C100 pr o vides a minimal component count and a cost-ef f ecti v e solution to the design and implementation of 10base - t standard netwo r k s . tpex plus pr o vides twisted-pair d r i v er and recei v er cir- cuit s , including on-board transmit digital predisto r tion, recei v er squelch, and an a ui po r t with pin-selecta b le sq e t est ena b l e . the d e vice pr o vides a number of ad- ditional f eature s , including link status indication with automatic twisted-pair recei v e pola r ity detection/ correction and indication ; pin-selecta b le recei v e threshold pro g ramming f or e xtended distance line lengths ; and recei v e car r ier sens e , t ransmit acti v e and collision present indication s . the d e vice pr o vides sepa r ate twisted-pair link statu s , p ola r ity statu s , recei v e , t ransmit, and collision outputs to d r i v e leds directl y .
amd 2 AM79C100 block diagram 16511b-1 polarity detection and auto correction line receiver and smart squelch link test state machine line driver and predistortion collision and loopback control line driver line driver jabber control led driver logic voltage controlled oscillator ci+ ci di+ di prdn/rst rext test 1 test2 txd+ txd txp+ txp rxd+ rxd do+ do xmt col rcv lnkst sqe test rxpol lrt line receiver and squelch circuit attachment unit interface (aui) twisted - pair interface related amd products part no. description am7996 ieee-802.3/ethernet/cheapernet tap transceiver am79c90 cmos local area network controller for ethernet tm (c-lance) am79c900 integrated local area communications controller tm (ilacc tm ) am79c940 media access controller for ethernet (mace tm ) am79c960 pcnet-isa single-chip ethernet controller (for isa bus) am79c961 pcnet-isa single-chip ethernet controller (with microsoft plug n play support) am79c965 pcnet-32 single-chip ethernet controller (for 386dx, 486 and vl buses) am79c970 pcnet-pci single-chip ethernet controller (for pci bus) am79c974 pcnet-scsi combination ethernet and scsi controller for pci systems am79c98 twisted-pair ethernet transceiver (tpex) am79c981 integrated multiport repeater plus tm (imr+ tm ) am79c987 hardware implemented management information base tm (himib tm )
AM79C100 3 connection di a gram plcc logic symbol 1 2 3 4 2 8 2 7 26 2 5 5 24 23 22 21 20 19 1 8 1 7 1 6 15 6 7 8 9 10 11 1 2 1 3 14 dv ss av ss col lnkst xmt dv ss do+ txp test2 sqe test lrt prdn/rst dv dd test1 av dd do rext rcv rxpol rxd rxd+ di+ di ci ci+ txd+ txd txp+ 16511 b -2 16511 b -3 do+ do di+ di ci+ ci sqe test test1 test2 rext prdn/rst txd+ txp+ txd txp rxd+ rxd l r t rxpol lnkst xmt rcv col AM79C100 d v dd a v dd d v ss a v ss attachment unit inter f ace ( a ui) t wisted- p air inter f ace
4 AM79C100 ordering inform a tion standa r d p r oducts amd standard products are a v aila b le in s e v e r al pa c kages and operating r ange s . the order number ( v alid combination) is f o r med b y a combination of the elements bel o w . v alid combinations v alid combinations list congurations planned to be sup- po r ted in v olume f or this d e vic e . consult the local amd sales of ce to con r m a v ailability of specic v alid combinations and to che c k on n e wly released combination s . AM79C100 j c device number/description AM79C100 twisted-pair ethernet transceiver plus (tpex plus) optional p r ocessing blank = standard processing oper a ting conditions c = commercial ( 0 c to +7 0 c) p a ck a g e type j = 28- pin plastic leaded chip carrier (pl 028) speed not applicable v alid combinations AM79C100 jc
AM79C100 5 pin description a v dd analog p o wer this pin supplies + 5 v to analog po r tions of th e tpex plus circuit r y . a v ss analog g r ound this pin is the g round re f erence f or analog po r tions of tpex plus circuit r y . ci+ , ci cont r ol in output a ui po r t dif f erential d r i v e r . col collision output , open drain this pin is d r i v en l o w while th e tpex plus is simulta- neously receiving data on the a ui do pins and the twisted-pair rxd pin s , indicating that a collision condi- tion e xist s . it is also d r i v en i f tpex plus enters the jab- ber condition due to e xcessi v e length of activity on the do pai r . in this cas e tpex plus will w ait f or a pe r iod of inactivity on do f or th e ?njab time of 250 to 750 m s , be f ore the 10 mhz patte r n on the ci pair is rem o v ed an d col retu r ns inacti v e . col will not be d r i v en du r ing sq e t est activity on the a ui ci pai r . in the l o w output stat e , the pin is capa b le of sinking a maxi m um of 12 ma and can be used to dri v e an le d . the col output is pulse stretched f or 20 to 62 ms after the end of colli- sion, to ensure led visibilit y . di+ , di data in output a ui po r t dif f erential d r i v e r . do+ , do data out input a ui po r t dif f erential recei v e r . d v dd digital p o wer this pin supplies + 5 v to digital po r tions of th e tpex plus circuit r y , including all t r ansmit d r i v er s . d v ss digital g r ound t w o pins pr o vide the g round re f erence f or digital por- tions o f tpex plus circuit r y , including all transmit d r i v ers and the status indication led d r i v er s . lnkst link status input/output , open drain when this pin is tied low, the internal link test re- ceive function is disabled, and the transmit and receive functions will remain active regardless of arriv- ing idle link pulses and data. tpex plus continues to generate idle link pulses irrespective of the status of this pin. as an output, this pin is driven low if the link is identi- fied as functional. however, if the link is determined to be nonfunctional due to missing idle link pulses or data packets, then this pin is not driven (internally pulled high). in the low output state, the pin is capable of sinking a maximum of 12 ma and can be used to drive an led. in the absence of an external drive, the pin is internally pulled high when inactive. lr t l o w receiv e threshold input , active l o w when this pin is tied l o w , the inte r nal twisted-pair re- cei v e thresholds are reduced b y 4.5 db from their o r ig- inal v alues (appr o ximately 3/5 of the no r mal 10base- t v alue) . wit h lr t in the high stat e , the unsquelch threshold f or the rxd circuit will be 300 mv to 520 mv peak . wit h lr t in the l o w stat e , the unsquelch threshold f or the rxd circuit will be 180 mv to 312 mv peak . in either cas e , the rxd circuit post unsquelch threshold will be appr o ximately one-half of the initial unsquelc h threshold. prdn/rst p o wer d o wn/reset input , active l o w d r iving this input l o w resets the inte r nal logic o f tpex plus and places the d e vice in a special p o w er d o wn mod e . in the p o wer d o wn/reset mod e , all output d r iv- ers are placed in their inacti v e stat e . rext external resistor input an e xte r nal precision resistor is connected bet w een this pin and a v dd in order to pr o vide a current re f er- ence f or the inte r nal v oltage-controlled oscillator (vco). rcv receive output , open drain this pin is dri v en l o w whil e tpex plus is receiving data on the twisted-pair rxd pins and is trans f er r ing the recei v ed signal onto the a ui di pai r . the output is l o w du r ing collision si m ultaneously with the col pin.
6 AM79C100 in the l o w output stat e , the pin is capa b le of sinking a maxim um of 12 ma and can be used to d r i v e an le d . th e rcv output is pulse stretched f or 20 ms to 62 ms after the end of reception, to ensure led visibilit y . rxd+ , rxd receive data input 10base- t po r t dif f erential recei v e r . rxpol receive p olarity input/output , open drain the twisted-pair recei v er is capa b le of detecting a re- cei v e signal with r e v ersed pola r ity (wi r ing error) . the rxpol pin is no r mally in the l o w stat e , indicating cor- rect pola r ity of the recei v ed signal . if the recei v er de- tects a recei v ed pa c k et with r e v ersed pola r it y , then this pin is not d r i v en (goes high) and the pola r ity of subse- quent pa c k ets is i n v e r ted . in the l o w output stat e , this pin can sink up to a maximum of 12 ma and is there f ore capa b le of d r iving an le d . this f eature can be disa b led b y strapping this pin l o w . in this cas e , the recei v e p ola r ity correction circuit is disa b led and the inte r nal recei v e signal remains non- i n v e r ted, irrespecti v e of the recei v ed signal. in the absence of an e xte r nal d r i v e , the pin is inte r nally pulled high when inacti v e . sqe test signal qualit y t est (hea r tbeat) ena b le input , active l o w the sq e t est function is ena b led b y tying this input l o w . when ena b led , tpex plus will send a 10 mhz b urst (hea r tbeat) on the ci lines after do has be- come inacti v e , indicating inte g r ity of the collision detec- tion and a ui circuit r y . sqe test should be disa b led f or repeater application s . in the absence of an e xte r nal d r i v e , the pin is inte r nally pulled high when inacti v e . test1 t est input , active high this pin should be tied l o w f or no r mal operation. test1 permits system-l e v el diagnostics to be per- f o r med . i f test1 is d r i v en high (whil e test2 is main- tained high) , tpex plus will enter the loopba c k t est mod e . the type of loopba c k is dete r mined b y the state of the sqe test pin . if sqe test is in the l o w state (station m a u) , tpex plus trans f ers data indepen- dently from do to th e txd/txp circuits and from rxd to the di circuit . if the sqe test is in the high state (repeater m a u), then data on the rxd circuit is trans- mitted ba c k onto th e txd/txp circuits and data on the do circuit is transmitted onto the di pai r . dur ing either test mod e , the collision detection and sq e t est functions are disa b led, and ci will remain idl e . link beat pulses will continue to be gene r ated nor- mally in the absence o f txd/txp output activit y , and the lin k t est recei v e state machine will be f orced into the link p ass stat e . the col pin will be d r i v en l o w when e v er a link beat pulse or transmit data activity commence s , and remain l o w du r ing the output activit y . the recei v e squelch will continue to operate on both the rxd and do input circuit s . in the absence of an e xte r nal d r i v e , the pin is inte r nally pulled l o w . test2 t est input , active l o w this pin should be tied high for normal operation. test2 is reserved for factory testing, and should be permanently tied high. in the absence of an e xte r nal d r i v e , the pin is inte r nally pulled high. txd+ , txd t ransmit data output 10base- t po r t dif f erential d r i v er s . txp+ , txp t ransmit predisto r tion output t ransmit w a v e f o r m dif f erential d r i v er f or predisto r tion. xmt t ransmit output , open drain this pin is dri v en l o w whil e tpex plus is receiving data on the a ui do pair and is transmitting data on the txd/txp pin s . the output is l o w du r ing collision si- m ultaneously with the col pin . in the l o w output stat e , the pin is capa b le of sinking a maxi m um of 12 ma and can be used to d r i v e an le d . the xmt output is pulse stretched f or 20 to 62 ms after the end of trans- mission, to ensure led visibilit y .
AM79C100 7 functional description th e t wisted- p air ethe r ne t t ranscei v er plus (tpex plus) complies with the requirements specied b y the ieee 802.3 standard f or the attachment unit inter f ace ( a ui) and the 10base-t standard f or a twisted-pair medium attachment unit (m a u) . tpex plus also imple- ments a n umber of f eatures in addition to the ieee 802.3 standard . an outline of the functions of the AM79C100 is gi v en bel o w . attachment unit interface (do , di , ci ) the a ui elect r ical and functional cha r acte r istics com- ply with those speci ed within the ieee 802.3 docu- ment s , sections 7 and 14 . the a ui pins can be wired to an isolation t r ans f o r me r , f or a remote m a u applica- tion, or directly to another d e vice ( e .g., am7992b se r ial inter f ace adapter), in the case of a local dte applica- tion . the end-of-pa c k et sq e t est function (hea r tbeat) can be disa b led to all o w the d e vice to be empl o y ed in a repeater application. t wisted- p ai r t ransmit function data t r ansmission to the 10base-t medium occurs when v alid a ui signals appear on the do dif f erential pai r . this data stream is routed to the dif f erential d r i v er circuit r y in th e txd an d txp pin s . the d r i v er circuit r y pr o vides the necessa r y elect r ical d r iving capability and the predisto r tion control f or transmitting signals o v er maxim um length twisted-pair ca b l e , as speci ed b y the ieee 802.3 10base- t standard . du r ing t r ansmission, data is looped ba c k to the di dif f erential circuit, indi- cating no r mal operation . the transmit function f or data output and loopba c k ope r ations meets the propagation del a ys and jitter specied b y the standard . du r ing nor- mal transmission, and pr o viding tha t tpex plus is not in a link f ail or j abber stat e , the xmt pin will be d r i v en l o w , and can be used to d r i v e a status led directl y . t wisted- p air receive function the recei v er complies with the recei v er speci cations of the ieee 802.3 10base-t standard, including noise imm unity and recei v ed signal rejection c r ite r ia (?ma r t squelch? . signals meeting these c r ite r ia appea r ing at the rxd dif f erential input pair are routed to the di output s . the recei v er function meets the propagation del a ys and jitter requirements specied b y the stan- dard . the recei v er squelch l e v el drops to appr o ximately half its threshold v alue after unsquelch to all o w recep- tion of minimum amplitude signals and to mitigate car- r ier f ade in the e v ent of w orst-case signal attenuation and crosstalk noise condition s . du r ing recei v e , the rcv pin is d r i v en l o w and can be used to d r i v e a sta- tus led directl y . note that the 10base-t standard denes the recei v e input amplitude at the e xte r nal media-dependent inter- f ace (mdi) . filter and t r ans f o r mer loss are not speci- ed . th e tpex plus recei v er squelch l e v els are de ned to account f or a 1 db inse r tion loss at 10 mhz, which is typical f or the type of recei v e lters/trans f o r mers rec- ommended (see als o t a b le 1). no r mal 10base- t -compati b le recei v e thresholds are empl o y ed when the lr t pin is inacti v e (high) . when th e lr t pin is e xte r nally pulled l o w , the l o w recei v e threshold option is i n v o k ed, and the sensitivity of the tpex plus recei v er is increased . this all o ws longer line lengths to be empl o y ed, e xceeding the 100 m tar- get distance of no r mal 10base- t (assuming typical 24 a wg ca b le) . the additional ca b le distance cont r i b utes directly to increased signal atte n uation and reduced signal amplitude at th e tpex plus recei v e r . h o w e v e r , from a system perspecti v e , making the recei v er more sensiti v e means that it is also more susceptible to e xtr aneous nois e , p r ima r ily caused b y coupling from co-resident se r vices (crosstalk) . f or this reason, it is recommended that when using the l o w recei v e threshold option, the se r vice should be installed on 4- pair ca b le onl y . multipair ca b les within the same outer sheath h a v e l o wer crosstalk attenuation, m a y all o w noise emitted from adjacent pairs to couple into the re- cei v e pai r , and be of sufcient amplitude to f alsely un- squelch th e tpex plu s . lin k t est function the lin k t est function is implemented as specied b y the 10base - t standard . du r ing pe r iods of t r ansmit pair inactivit y , ?ink beat pulses will be sent pe r iodically o v er the twisted-pair medium to all o w constant monitor- ing of medium integ r it y . when the lin k t est function is ena b led, the absence of link beat pulses and recei v e data on the rxd pair will cause th e tpex plus to go into a link f ail stat e . in the link f ail stat e , data t r ansmission, data reception, data loopba c k, and collision detection functions are disa b led and remain disa b led until v alid data or >5 consecuti v e link pulses appear on the rxd pai r . du r ing link f ail, the lnkst pin is inte r nally pulled high . when the link is identi ed as functional, the lnkst pin is dri v en l o w , and is capa b le of directly d r iving a ?ink ok le d . in order to interoperate with systems that do not implement lin k t est, this function can be disa b led b y g rounding the lnkst pin . with lin k t est disa b led, the data d r i v e r , recei v e r , and loopba c k function s , as w ell as collision detection, remain ena b led irrespecti v e of the presence or absence of data or link pulses on the rxd pai r . p olarity detection and r e ve r sal the tpex plus recei v e function includes the ability to i n v e r t the pola r ity of the signals appea r ing at the rxd pair if the polarity of the recei v ed signal is r e v ersed (such as in the case of a wi r ing error) . this f eature al- l o ws data pa c k ets recei v ed from a r e v erse-wired rxd input pair to be corrected in th e tpex plus p r ior to t r ans f er to the dte via the a ui inter f ace (di ) . the
8 AM79C100 pola r ity detection function is acti v ated f oll o wing reset or link f ail, and will r e v erse the recei v e pola r ity based on both the pola r ity of a n y pr e vious link beat pulses and the pola r ity of subsequent pa c k ets with a v alid end tr ansmit delimiter (etd) . when in the link f ail stat e , tpex plus will recogni z e link beat pulses of either positi v e or negati v e pola r it y . exit from the link f ail state is caused b y the reception of 5 to 6 consecuti v e link beat pulses of identical polar- it y . on ent r y to the link p ass stat e , the pola r ity of the last 5 link beat pulses is used to dete r mine the initial re- cei v e pola r ity con gu r ation and the recei v er is recong- ured to subsequently recogni z e only link beat pulses of the pr e viously recogni z ed pola r it y . this link pulse algo- r ithm is empl o y ed only until sfd pola r ity dete r mination is mad e , as desc r ibed later in this section. p ositi v e link beat pulses are dened as recei v ed signal with a positi v e amplitude greater than 520 mv (lr t = high) with a pulse width of 60 ns to 200 n s . this posi- ti v e e xcursion m a y be f oll o wed b y a negati v e e xcursion. this denition is consistent with the e xpected recei v ed signal at a correctly wired recei v e r , when a link beat pulse that ts the template of figure 14-12 in the 10base- t standard is generated at a transmitter and passed through 100 m of twisted-pair ca b l e . negati v e link beat pulses are dened as recei v ed sig- nals with a negati v e amplitude g reater than 520 mv ( lr t = high) with a pulse width of 60 ns to 200 n s . this negati v e e xcursion m a y be f oll o wed b y a positi v e e xcursion . this denition is consistent with the e x- pected recei v ed signal at a r e v erse-wired recei v e r , when a link beat pulse that ts the template of figure 14-12 in the 10base - t standard is gene r ated at a t r ansmitter and passed through 100 m of twisted-pair ca b l e . the pola r ity detection/correction algo r ithm will remain ? r med until t w o consecuti v e pa ck ets with v alid etd of identical pola r ity are detected . whe n ? r med , the re- cei v er is capa b le of changing the initial or pr e vious po- la r ity congu r ation based on the most recent etd pola r it y . on receipt of the rst pa c k et with v alid etd f oll o wing reset or link f ail , tpex plus will utili z e the in f erred po- la r ity in f o r mation to congure its rxd input, regard- less of its pr e vious stat e . on receipt of a second pa c k et with a v alid etd with correct pola r it y , the detection/cor- rection algorithm wil l ?o c k in the recei v ed pola r it y . if the second (or subsequent) pa c k et is not detected as con r ming the pr e vious pola r ity decision, the most re- cently detected etd pola r ity will be used as the de f ault. note that pa c k ets with i n v alid etd h a v e no ef f ect on updating the pr e vious pola r ity decision . once two con- secuti v e pa c k ets with v alid etd h a v e been recei v ed, tpex plus will disa b le the detection/correction algorithm until either a link f ail condition occurs or prdn/rst is asse r ted. dur ing pola r ity r e v ersal, the rxpol pin is inte r nally pulled high . du r ing no r mal pola r ity condition s , the rxpol pin is dri v en l o w , and is capa b le of directly d r iving a p ola r ity ok led using an integrated 12 ma d r i v e r . if desired, the p ola r ity r e v ersal function can be disa b led b y grounding the rxpol pin. t wisted- p air interface status three outputs (xmt , rcv , and col ) indicate whether th e tpex plus is t r ansmitting ( a ui to twisted-pair), re- ceiving (twisted-pair to a ui), or in a collision state with both functions acti v e si m ultaneousl y . th e tpex plus will p o wer up in the link f ail stat e . the no r mal algo r ithm will apply to all o w it to enter the link p ass stat e . on p o wer u p , the xmt , rcv , and col led d r i v ers acti v ate f or 20 ms to 62 ms as a lamp test f ea- tur e , and will then go to their inacti v e state unti l tpex plus enters the link p ass stat e . in the link p ass stat e , t r ansmit or recei v e activity that passes the pulse-width/amplitude requirements of the do or rxd inputs will be indicated b y the xmt or rcv pin, respecti v el y , going acti v e . xm t , rc v , and col are all asse r ted du r ing a collision. in the link f ail stat e , xmt , rcv , and col are disa b led . in j a b ber detect mod e , tpex plus will acti v ate the col d r i v e r , disa b le the xmt d r i v er (regardless of do activity), and all o w the rcv d r i v er to indicate the cur- rent state of the rxd pai r . if there is no recei v e activity on rxd , only col will be acti v e du r ing j abber detect. if there is rx d activit y , both col and rcv will be acti v e . all three outputs are acti v e l o w and inco r po r ate 12 ma d r i v e capability with 20 ms to 62 ms pulse stretch circuit r y , to e xtend the e v ent to ensure led visibilit y . collision detect function si m ultaneous car r ier sense (presence of v alid data signals) b y both the a ui do pins and the twisted-pair rx d pins constitutes a collision, there b y causing a 1 0 mhz signal to be asse r ted on the ci output pai r , and the col output to be acti v ated . the ci output meets the d r i v e requirements f or the a ui inter f ac e . this 1 0 mhz signal will remain on the ci pair until one of the t w o colliding states changes from acti v e to idl e . dur ing the collision condition, data presented on the di pair will be sourced from the rxd input . at the end of collision, the data presented on the di pair will be sourced from the last remaining acti v e input, either rxd or do . the ci output pair st a ys high f or 2 bit times at the end of a collision, decreasing to the idle l e v el within 80 bit times after the last t r ansition . the xmt , rcv , and col pins are d r i v en l o w du r ing collision.
AM79C100 9 signal quality er r or (sqe ) t est (hea r tbeat) function when the sqe test pin is d r i v en l o w , tpex plus will routinely e x ercise the collision detection circuit r y b y gene r ating an sq e t est message at the end of e v e r y transmission . this signal is a self-test indication to the dte that the m a u collision circuit r y is functional and the a ui ca b le/connection is intact . an sq e t est mes- sage consists of a 10 mhz signal on the ci pair with a du r ation of 5 to 15 bit times (500 ns to 1500 ns) . when ena b led, an sq e t est will occur at the end of e v e r y t r ansmission, sta r ting 6 to 16 bit times (600 ns to 160 0 ns) after the last t r ansition of the t r ansmitted sig- nal . f or repeater applications, the sq e t est function can be disa b led b y tying the sqe test pin high or b y le a ving it disconnected . the col output will remain in- acti v e du r ing the sq e t est message on ci . jabber function the j a b ber function inhibits the twisted-pair transmit function o f tpex plus if the do circuit is acti v e f or an e xcessi v e pe r iod (20 ms to 150 ms) . this pr e v ents a n y one node from dis r upting the netwo r k due to a ?tu c k on or f aulty t r ansmitte r . if this maxi m um trans- mit time is e xceeded, th e tpex plus transmitter cir- cuit r y is disa b led and a 10 mhz signal is d r i v en onto the c i pai r . once the t r ansmit data stream is rem o v ed from the do input pai r , a n ?njab time of 250 ms to 750 ms will elapse be f ore th e tpex plus rem o v es the 10 mhz signal from the c i pair and re-ena b les the tr ansmit circuit r y . when ja b ber is detected , tpex plus will acti v ate the col d r i v e r , disa b le the xmt d r i v er (regardless of do activity), and all o w the rcv d r i v er to indicate the current state of the rxd pai r . if there is no recei v e ac- tivity on rxd , only col will be acti v e du r ing j abber detect . if there is rxd activit y , both col and rcv will be acti v e . p o wer d o wn in addition to on-board p o wer-on-reset circuit r y , the prdn/rst pin is used as the master reset f o r tpex plu s . prdn/rst m ust be d r i v en l o w f or a minimum of 2 m s f or reset to occu r . the prdn/rst pin can also be used to put th e tpex plus into an inacti v e o r ?leep stat e , causing the d e vice to consume less p o we r . this f eature is useful in batte r y-p o wered or l o w-duty-cycle system s . d r iving prdn/rst l o w resets the inte r nal logic o f tpex plus and places the d e vice into idle mod e . in this mod e , the twisted-pair d r i v er pins (txd , tx p ) are d r i v en l o w , the a ui pins (ci , di ) are pulled to a v dd , the lnkst and rxpol pins are in the inacti v e stat e , and the xmt , rcv , and col pins are in the high-impedance stat e . tpex plus will remain in idle mode as long as prdn/rst is asse r ted . f oll o wing the r ising edge of the signal on prdn/rst , tpex plus will remain in the reset state f or up to 10 m s . immediately after the reset condition is rem o v ed , tpex plus will d r i v e the xmt , rcv , and col outputs l o w f or 2 0 ms to 62 ms as a lamp test f eatur e , and will be f orced into the link f ail stat e . tpex plus will m o v e to the link p ass state only after 5 to 6 link beat pulses and/or a single recei v ed message is detected on the rxd pai r . t est modes tpex plus implements t w o types of loopba c k test modes suita b le f or station (dte) or repeater applica- tion s . the test mode is entered b y d r iving th e test1 pin high . th e test2 pin is intended f or f acto r y test only and should be tied high f or test mode or no r mal ope r ation . the t w o a v aila b le test modes are: 1 . station (dte) : sqe test pin l o w . data recei v ed on the do input pair is t r ansmitted onto th e txd and txp output pair s , and data recei v ed on the rxd input pair is t r ansmitted onto the di output pai r . 2 . repeater : sqe test pin high . data recei v ed on the do input pair is looped ba c k onto the di out- put pai r , and data recei v ed on the rxd pair is looped ba c k and retransmitted on the twisted-pair d r i v ers (txd an d txp pairs). in both mode s , tpex plus will be f orced into the link p ass state and will not enter the link f ail stat e , regard- less of rxd inactivit y . the f oll o wing functions are dis- a b led : jabber circuit, collision detection, and collision oscillato r . the functions that remain ena b led are : the do and rxd squelch circuits, xmt and rcv out- put s , link beat pulse generation, and pola r ity detection/ correction . in addition, in both mode s , the col pin (not used to indicate collision du r ing test modes) will go ac- ti v e f or the duration of a n y transmit activity on the txd /txp pair s , pr o viding a leading high-to-l o w edge indicating the sta r t of pa c k et t r ansmission or link beat pulse gene r ation . upon e xiting either of the test mode s , the lin k t est state machine will be f orced into the link f ail stat e . rxpol m a y be pulled l o w and recei v e pola r ity correction will be disa b led. tpex plus external components figure 1 sh o ws a typical twisted-pair po r t e xte r nal com- ponents schematic . the resistors used should h a v e a 1% tole r ance to ensure interope r ability with 10base - t -compliant netwo r k s . the lters and pulse trans f o r mers are necessa r y d e vices that h a v e a major in uence on the per f o r mance and compliance of a tpex plus-based m a u . specicall y , the t r ansmitted w a v e f o r ms are he a vily in uenced b y lter cha r acte r is- tics and the twisted-pair recei v ers empl o y s e v e r al
1 0 AM79C100 crite r ia to conti n uously monitor the incoming signal s amplitude and timing cha r acte r istics to dete r mine when and if to asse r t the inte r nal car r ier sens e . f o r these reason s , it is c r ucial that the v alues and tole r ances of the e xte r nal components be as speci ed. s e v er al manu f acturers produce a module that com- bines the functions of the t r ansmit and recei v e lters and the pulse t r ans f o r mers into one pa c kag e . note: the lter/transformer module shown is available from the following manufacturers: belfuse, tdk, pulse engineering, pca, valor electronics , and nano pulse. figure 1. t ypica l t wisted- p air p o r t external components 16511 b -4 57.6 324.0 768.0 57.6 324.0 100 w AM79C100 tpex plus txd+ txp+ txd txp rxd+ rxd xmit filter recv filter 1:1 1:1 td+ td rd+ rd t wisted- p air ca b le module

amd 12 AM79C100 16511b-6 note : 1. during loopback, the col pin does not indicate collision, but instead provides indication of txd /txp activity. for details, refer to the section titled test modes. repeater loopback test mode sqe tes t test 1 test2 rc v co l xmt do ci di txd?txp rxd hig h hig h high station/dte loopback test mode sqe tes t test1 test2 rc v co l xmt do ci di txd?txp rxd lo w hig h high note 1 note 1 figure 3. AM79C100 tpex plus loopback operation
amd 13 AM79C100 system applications aui connector xmt filter rcv filter rj45 connector anlg gnd anlg +5 v pulse transformer avss avdd 0.1? filter and transformer module 40.2 w 40.2 w note 1 note 2 note 3 td+ td rd+ rd 1 2 3 6 AM79C100 link ok dgtl +5 v anlg +5 v do- di+ di- ci+ ci- do+ test1 rext test2 pwdn/rst sqe test optional enable heartbeat dgtl gnd optional enable low threshold optional 0.01? dvss dvdd col xmt rcv optional dgtl gnd dgtl +5 v dgtl gnd 0.1? 24.3 k w 1% txp+ txd- txp- txd+ rxd+ rxd- lnkst lrt xmt col rcv rxpol rx pol ok 4.7? 0.1 ? anlg gnd 57.6 w 100.0 w 324.0 w 768.0 w 324.0 w 57.6 w 116511b-7 notes: 1. compatible filter modules, with a brief description of package type and features are included in table 1 of this section. 2. the resistor values are recommended for general purpose use, and should allow compliance to the 10base-t specification for template fit and jitter performance. however, the overall performance of the transmitter is also affected by the transmit filter configuration. 3. compatible aui transformer modules, with a brief description of package type and features are included in table 2 of this section. figure 4. AM79C100 stand alone mau system application anlg gnd
amd 14 AM79C100 table 1. tpex plus compatible media interface modules manufacturer part # package description bel fuse a556-2006-de 16-pin 0.3 dil transmit and receive filters and transformers bel fuse 0556-2006-00 14-pin sip transmit and receive filters and transformers bel fuse 0556-2006-01 14-pin sip transmit and receive filters, transformers and common mode chokes valor electronics pt3877 16-pin 0.3 dil transmit and receive filters and transformers valor electronics pt3983 8-pin 0.3 dil transmit and receive common mode chokes valor electronics fl1012 16-pin 0.3 dil transmit and receive filters and transformers, transmit common mode choke nan o pulse np6612 16-pin 0.3 dil transmit and receive filters, transformers and common mode chokes nano pulse np6581 8-pin 0.3 dil transmit and receive common mode chokes nan o pulse np6696 24-pin 0.6 dil transmit and receive filters, transformers and common mode chokes tdk tl a 470 14-pin sip transmit and receive filters and transformers tdk him3000 24-pin 0.6 dil transmit and receive filters, transformers and common mode chokes puls e engineering pe65421 16-pin 0.3 dil transmit and receive filters and transformers puls e engineering supra 1.1 16-pin 0.5 dil transmit and receive filters and transformers, transmit common mode choke bel fuse 0556-6392-00 16-pin 0.5 dil transmit and receive filters, transformers, and common mode chokes table 2. AM79C100 tpex plus compatible aui transformers manufacturer part # package description bel fuse a553-0506-ab 16-pin 0.3 dil 50 m h valor electronics lt6031 16-pin 0.3 dil 50 m h tdk tl a 100-3e 16-pin 0.3 dil 100 m h puls e engineering pe64106 16-pin 0.3 dil 50 m h
amd 1 5 AM79C100 absolute maximum ratings storage temperature: C65 c to +150 c . . . . . . . . . . . ambient temperature under bias: 0 c to +70 c . . . . supply voltage to av ss or dv ss (av dd , dv dd ): C0.3 v to +6 v . . . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices temperature ( t a ): 0 c to +70 c . . . . . . . . . . . . . . . . supply voltages (av dd , dv dd ): +5 v 5 % . . . . . . . . . all inputs within the range: av ss C0.5 v v in av dd + 0.5 v, or dv ss C0.5 v v in dv dd +0.5 v operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating range unless otherwise specified parameter symbol parameter description tes t conditions min max unit digital input voltage v il input low voltage 0.8 v v ih input high voltage 2.0 v digital output voltage v ol output low voltag e i ol = 12 ma (open drain) 0.4 v ( xmt , rcv , col , lnkst and rxpol) digital input leakage current i ill input leakage curren t dv ss < v in < dv dd 10 m a (prdn/rst) i ild input leakage current dv ss < v in < dv dd 500 m a (lnkst/rxpol, output inactive) digital output leakage current i old output leakage curren t dv ss < v in < dv dd 10 m a ( xmt , rcv , col ) aui i iaxd input current at do+, doC av ss < vin < av dd C500 500 m a v aicm do open circuit input i in = 0 v a v dd C3.0 av dd C1.0 v common mode voltage (bias) v aidv differential mode input av dd = +5 v C2.5 +2.5 v voltage range (do ) v asq do squelch threshold C160 C275 mv v ath do switching threshold (not e 1) C35 +35 mv v aod differential output voltage r l = 78 w 620 1100 mv |(di+)C(diC)| or |(ci+)C(ciC)| v aodi di & ci r l = 78 w C25 +25 mv differential outpu t (note 1) voltage imbalance v aod off di & ci r l = 78 w C40 +40 mv differential idle output voltage i aod off di & ci r l = 78 w C1 1 m a differential idle output current (note 1) v aocm di & ci common r l = 78 w 2.5 av dd v mode output voltage
amd 1 6 AM79C100 dc characteristics (continued) parameter symbol parameter description tes t conditions min max unit twisted pair interface i irxd input current at rxd av ss < v in < av dd C500 500 ua r rxd rxd differential input (note 1) 10 k w resistance v tivb rxd+, rxdC open circui t i in = 0 ma av dd C3.0 av dd C1.5 v input voltage (bias) v tidv differential mode input av dd = +5 v C3.1 3.1 v voltage range (rxd ) v tsq+ rxd positive sinusoi d 300 520 mv squelch threshold (peak) 5 mh z < f < 10 mhz v tsqC rxd negative sinusoid C520 C300 mv squelch threshold (peak) 5 mh z < f < 10 mhz v ths+ rxd post-squelch positive sinusoid 150 293 mv threshold (peak) 5 mh z < f < 10 mhz v thsC rxd post-squelch negative sinusoid C293 C150 mv threshold (peak) 5 mh z < f < 10 mhz v ltsq+ rxd positive lrt = low 180 312 mv squelch threshold (peak) v ltsqC rxd negative lrt = low C312 C180 mv squelch threshold (peak) v lths+ rxd post-squelch positive lrt = low 90 175 mv threshold (peak) v lthsC rxd post-squelch negative lrt = low C175 C90 mv threshold (peak) v rxdth rxd switching threshold (note 1) C60 60 mv v txh txd and txp dv ss = 0 v dv dd C0.6 dv dd v output high voltage (not e 2) v txl txd and txp dv ss = +5 v d v ss dv ss + 0.6 v output low voltage (not e 2) v txi txd and txp differential C40 40 mv output voltage imbalance v txoff txd and txp dv dd = +5 v C40 40 mv idle output voltage r tx txd and txp differential (note 1) 40 w driver output impedance i irext input current at rext pin r ext = 24.3 k w 1% 120 m a av dd = +5 v power supply current i dd power supply current prdn/rst = high 40 ma (idle) dv dd = av dd = +5 v power supply current prdn/rst = low 95 ma (transmittingno tp load) power supply current prdn/rst = high 150 ma (transmittingwith tp load) dv d d = av dd = +5 v i ddprdn power supply current prdn/rst = low 4 m a in power down mode notes: 1. parameter not tested. 2. uses switching test load.
amd 1 7 AM79C100 switching characteristics over commercial operating ranges parameter symbol parameter description min max unit transmit timing t pwodo do pulse width accept/ v do > |v asq max| 15 35 ns reject threshold (not e 3) t pwkdo do pulse width maintain/ v do > |v asq max| 105 200 ns turn-off threshold (not e 4) t ton transmit start up delay 300 ns t tsd transmit static propagation 120 ns delay (do to txd ) t tetd transmit end transmit delimiter 250 450 ns t tr transmitter rise time 10 ns (10% to 90%) t tf transmitter fall time 10 ns (90% to 10%) t tm transmitter rise and fall 4 n s time mismatch t thd d o - to txd+ - steady state t tsd C 1.0 t tsd + 1.0 ns and txdC delay (note 1) t tld do to txd+ steady state t tsd C 1.0 t tsd + 1.0 ns and txdC - delay (note 1) t thdp do - to txp+ steady state t tsd + 40 t tsd + 60 ns and txpC - delay (note 1) t tldp do to txp+ - steady state t tsd + 40 t tsd + 60 ns and txpC delay (note 1) t xmton xmt asserted delay 100 ns t xmtoff xmt de-asserted delay 20 62 ms t perlp idle signal period 8 2 4 m s t pwlp link beat pulse width (note 1) 75 120 ns t pwplp predistortion idle link (note 1) 40 60 ns beat width t ja transmit jabber 20 150 ms activation time t jr transmit jabber 250 750 ms reset time t jrec transmit jabber (not e 1) 1.0 C m s recovery time (minimum time gap between transmitted packets to prevent jabber activation) t dodion do to di startup delay 300 ns t dodisd do to di static propagation 100 ns delay test conditions
amd 1 8 AM79C100 switching characteristics (continued) parameter symbol parameter description min max unit receive timing t pwkrd rxd pulse width maintain/ v in >v ths min 136 200 ns turn-off threshold (not e 5) t ron receiver start up delay tested with 5 mh z 200 400 ns (rxd to di ) sinusoid t rvb first validly timed bi t t ro n + 100 ns on di t rsd receiver static propagation 70 ns dela y (rxd to di ) t retd di end of transmission 200 ns t rhd rxd - to di+ - (not e 1) t rsd C 2.5 t rsd + 2.5 ns and diC delay t rld rxd to di+ (not e 1) t rsd C 2.5 t rsd + 2.5 ns and diC - delay t rr di+, diC, ci+, ciC rise time 5 n s (10% to 90%) t rf di+, diC, ci+, ciC fall time 5 n s (10% to 90%) t rm di and ci rise and fal l 2 n s time mismatch (t rr C t rf ) t rcvon rcv asserted delay t ron C 50 t ron + 100 ns t rcvoff rcv de-asserted delay 20 62 ms collision detection and sqe test t con collision turn-on 500 ns delay (ci ) t coff collision turn-off 500 ns delay (ci ) t per collision period (ci ) 8 7 117 ns t cpw collision output pulse width 40 60 ns (ci ) t sqed sqe test delay time 600 1600 ns t sqel sqe test lengt h 500 1500 ns t colon col asserted delay t con C 50 t con + 100 ns t coloff col de-asserted delay 20 62 ms notes: 1. parameter not tested. 2. uses switching test load. 3. do pulses narrower than t pwodo (min) will be rejected; pulses wider than t pwodo (max) will turn internal do carrier sense on. 4. do pulses narrower than t pwkdo (min) will maintain internal do carrier sense on; pulses wider than t pwkdo (max) will turn internal do carrier sense off. 5. rxd pulses narrower than t pwkrd (min) will maintain internal rxd carrier sense on; pulses wider than t pwkrd (max) will turn internal rxd carrier sense off. test conditions
amd 1 9 AM79C100 switching test circuits dv dd txd+ 294 w 100 pf txdC dv ss 29 4 w test point 16511b-8 dv dd txp+ 715 w 100 pf txpC dv ss 71 5 w includes test jig capacitance test point includes test jig capacitance 16511b-9 twisted pair transmit test circuit av dd di+ diC ci+ ciC 154 w 50 pf av ss 52.3 w test point 16511b-10 aui transmit test circuit
amd 2 0 AM79C100 key to switching waveforms ks000010 must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs
amd 21 AM79C100 switching waveforms transmit timing 16511b-11 transmit link beat pulse 16511b-12 do t pwkdo t xmtoff txp+ txd- txp- txd+ tetd t v ath+ v ath- t ton t xmton t tf t tr t pwodo t thdp t tldp v asq(min) v asq(max) xmt di t dodion t dodisd t pwkdo txd+ txp+ txd- txp- t pwlp t perlp t pwplp
amd 22 AM79C100 switching waveforms 16511b-13 receive timing di+ rxd retd t t rcvoff t rcvon t rf t rr t ron t rhd v tsq v tsq+ di rcv t rf t rr t rld t pwkrd t pwkrd 16511b-14 receive thresholds rxd v tsq v tsq+ v ths v ths+ rxd v ltsq v ltsq+ v lths v lths+
amd 23 AM79C100 switching waveforms 16511b-15 t coff t colon t coloff t con t cper t cpw rxd do ci+ ci col collision timing 16511b-16 col = 1 do ci+ ci t sqel t sqed sqe test timing
trademarks copyright ? 1998 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am186, am386, am486, am29000, b imr, eimr, eimr+, gigaphy, himib, ilacc, imr, imr+, imr2, isa-hub, mace, magic packet, pcnet, pcnet- fast , pcnet- fast +, pcnet-mobile, qfex, qfexr, quasi , quest, quiet, taxichip, tpex, and tpex plus are trademarks of advanced micro devices, inc. microsoft is a registered trademark of microsoft corporation. product names used in this publication are for identitcation purposes only and may be trademarks of their respective companies.

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